I am against _moving_ the bzero cost in a not obvious
place. Removing it completly also automagically saving data-cache
is a completly different thing and I would like to do that of
course (unfortunately only on machines that have the magic
NCR53c8xx).
Andreas, let me say it for the 1,000th time.
Some cpus in this world allow data cache bypassing to be done during
loads and stores, in fact optimal bcopy/bzero is implemented using
these facilities (especially on chips where the load/store moves an
entire cache line at a time). PPC and Sparc allow this for example.
There is no cache pollution (and with some slick tricks I even avoid
any TLB side-effects during page zero and copy operations on
UltraSparc).
So in these cases, what is this "cost" you keep complaining
about? Yes, perhaps most broken x86 chips don't allow this
to happen (but I bet their microcode can do these sorts of
things if we ever reverse engineered that), but expect more
cpus in the future to provide these sorts of things, not less.
Most L1 data caches are not write-allocate anyways.
Later,
David S. Miller
davem@redhat.com
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