The test is a simple ping-pong latency test between two machines. End-
to-end hardware latency (polling mode, without interrupts) is <8uS.
On a UP system, blocking end-to-end latency is <17uS, so we can catch
an interrupt, schedule, and wake up in 9uS. That overhead goes up to
43uS on an SMP machine, for a total end-to-end of 50uS.
A bit more investigation: smp_processor_id() shows that interrupt
delivery is strictly alternating between the two CPUs, and that the
task is waking up on the interrupted CPU, and thus thrashing back and
forth between the two CPUs.
Running SMP with maxcpus=1 cuts latency by 10uS (PII/400), and cuts the
interrupt-to-schedule() time from 6700 clocks to about 4400. (and I
guess the 1300-clock difference is a gross underestimate, as the cache
misses will continue all the way up to user level)
So it looks like I'm stuck with most of the SMP overhead, but if I could
get rid of the CPU thrashing I could still save 10uS. Is there any
way to use bottom halves here to make things better?
-- ............................................................................ Peter Desnoyers 162 Pleasant St. (617) 661-1979 pjd@fred.cambridge.ma.us Cambridge, Mass. 02139 (978) 461-0402 (work) pjd@giga-net.com- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/