Oh, I recognize the code is _ancient_, almost two years old. But the
point of my post with those excessively long quotes from Intel is that
on the P6 , Intel doesn't guarantee LOCK for write-back cached addresses!
> the NMI oopser running on all SMP boxes unconditionally, which shouldYes. I have had one ooops I really ought to look up in System.map .
I was somewhat surprised that both CPU's oops'd simultaneously at the
same EIP.
> i've disabled the above workaround in smp-2.3.29-B2 (attached, againstI'm still at 2.2.13, and really ought to step up to 2.3 .
> - adds the 'movb $0, %0' spin_unlock() variant, now that Intel has
> clarified the P6 core's cache-coherency behavior.My understanding is that you don't have a chance of atomicity unless
the address is aligned [so it won't cross cache lines]. I've observed
gcc being very poor at alignment, inserting .align 2 when .align 4 would
have been better. And gas using the last given .align when there are
multiples. So movb is a good idea. Or is there something else?
> - fixed the annoying 'APIC error ...' messages on rebootIs this related to the 82443BX erratum of hanging on reboot when
>
> - cleaned up the reboot path, clean APIC/IOAPIC state after reboot
Is this related to the documented 82443BX erratum of hanging on
reboot when DRAM refresh is in progress?
> - the error codes in 'APIC error ...' messages are now analyzed andI've never seen any of these.
-- Robert author `cpuburn` http://users.ev1.net/~redelm
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