Re: spin_unlock optimization(i386)

Stefan Monnier (monnier+misc/ads@tequila.cs.yale.edu)
Tue, 30 Nov 1999 06:36:29 -0500

> volatile int valid=0, value;
>
> CPU0:
> while(valid==0);
> output=value;
>
> CPU1:
> value=45;
> valid=1;
>
> Now CPU0 sees no dependency between the two reads, so it's free to use a
> speculative read for 'value' -- one that actually took place on the bus
> before the read inside the while loop.

Nope. Because when CPU0 reads 1 from valid, the value read is still
not retired (i.e. committed) and at this point it sees that value is
set to 45 (because it couldn't have seen valid=1 before seeing value=45
since writes are not reordered). So it will re-exec the read of value
(because the not-yet-committed-read is still around and its address
is matched to the incoming writes, allowing to detect such problems).

Now I don't know if this is part of x86 or only P6 since
supposedly the P6 provides a slightly stronger consistency model.

Also this solves the present case but not the one I sent earlier
because no CPU needs to see any of the other's writes, so the
instructions can all be retired before any communication takes place.

Stefan

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