> Each time you write code that runs SMP threaded you must insert the proper
> barriers and you must consider each case separately. That's why writing
> SMP threaded code is harder ;).
Of course. My point is that where you put the barriers depends on the
how strong the ordering model of the processor is. And since most of us
don't have data books for all the current CPUs, it would be helpful to
know what the lowest common denominator was. What is the weakest ordering
model the kernel will support?
-- "Love the dolphins," she advised him. "Write by W.A.S.T.E.."
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