The cpu cannot undo retired instructions. (they are retired, ie the cpu has
finished that instructions, it has already forgotten that it has executed
that instruction, side-effects of the instruction are externally observable)
read instructions are
* executed _before_ they retire.
* it seems that the cpu reevaluates read instructions if a write instruction
arrives over the memory bus (AFAICS we do not rely on this)
write instruction are
* _never_ visible before the instruction retires.
* even after they retire, they are not immediately externally visible
[obvious: the FSB runs at 100 MHz, the core at 500+Mhz: there are at least 4
cycles before the instruction could become visible. In reality, this is
_far_ longer]
> But if a read happens between XXX and YYY, then - to preserve
> processor ordering - the hardware should invalidate [...]
processor ordering is only enforced on single cpu systems.
[eg: 2 cpus execute a conflicting write operation in _exactly_ the same cpu
tick, which one should win?]
--
Manfred
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