It seems that some implementation of this interface only enforces a
barrier after the IO/MMIO. If I am right, that means that if we want, for
example, a STORE to memory followed by a writeX to be observed in that
order by a PCI device, we must insert an explicit barrier between the
STORE to memory and the writeX, for architectures that implements some
weak ordering. By the way, this is often the case in PCI device drivers.
If these macros are intended to make Intel-targetted device drivers to
transparently work on arch like PPC, they should actually guarantee the
Intel ordering of IO or UC, in my opinion. By the way, I donnot think
Intel-only-thought driver to work this way on other archs, but think that
the driver writers must be aware of ordering.
But since kernel guys seem to think this does work so, I donnot want to
make effort for architectures != Intel.;-)
Can somebody elaborate, especially about readX/writeX implementation for
PPC. Thanks.
Gérard.
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