Re: [PATCH 2/3] dt-bindings: net: Document GBETH bindings for Renesas RZ/V2H(P) SoC

[Russell King (Oracle)]

On Sun, Mar 02, 2025 at 08:41:39PM +0000, Lad, Prabhakar wrote:
> Hi Andrew,
> 
> On Sun, Mar 2, 2025 at 7:25 PM Andrew Lunn <andrew@xxxxxxx> wrote:
> >
> > > +  clock-names:
> > > +    items:
> > > +      - const: stmmaceth
> > > +      - const: pclk
> > > +      - const: ptp_ref
> > > +      - const: tx
> > > +      - const: rx
> > > +      - const: tx-180
> > > +      - const: rx-180
> >
> > As Russell said in an older thread, tx and tx-180 are effectively the
> > same clock, but with an inverter added. You should be able to arrange
> > the clock tree that if you enable tx, it also enables tx-180 as a
> > parent/sibling relationship.
> >
> I can certainly do that, but not sure in the DT we will be describing
> the HW correctly then. I'll have to hide *-180  clocks In the DT and
> handle and turning on/off these clocks in the clock driver.
...
>              clocks =  <&cpg CPG_MOD 0xbd>,
>                             <&cpg CPG_MOD 0xbc>,
>                             <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
>                             <&cpg CPG_MOD 0xb8>,
>                             <&cpg CPG_MOD 0xb9>,
>                             <&cpg CPG_MOD 0xba>,
>                             <&cpg CPG_MOD 0xbb>;

Your SoC designer really implemented the 0° and 180° as two separate
independently controllable clocks?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!