RE: [PATCH v2 1/3] dt-bindings: lgm-dma: Added intel,dma-sw-desc property.

[Yi xin Zhu]

Hi Krzysztof,

On 15/08/2025 18:40, Krzysztof wrote:
> 
> 
> What is a "SoC level configuration"?
> 
> From your explanation 1+2 it feels like consumer chooses it. Where is a full DTS
> showing all this?
> 
> 
> > of the DMA instances work in hardware descriptor mode while other DMA
> > instances work in software descriptor mode or all in HW/SW mode.
> >
> 
> Best regards,
> Krzysztof

In the LGM SoC,  The DMA instances are default connected to CBM(central buffer manager) to automate the DMA descriptors.  
It can also be detached from CBM to use it in different use cases individually.

In the HW descriptor case,  the device tree would be like:

dma1tx: dma-controller@e7300000 {
      compatible = "intel,lgm-dma1tx";
      reg = <0xe7300000 0x1000>;
      ...
      #dma-cells = <3>;
      intel,dma-poll-cnt = <16>;
};

cbm: cbm@e1000000 {
   dmas = <&dma1tx 0 0 64>, <&dma1tx 1 0 64> ... <&dma1tx 15 0 64>;
   
};

DMA HW feature, desc_fod(descriptor fetch on demand) and desc_in_sram are turned on in the DMA controller in this case.
These HW features are defined in platform data in the existing DMA driver as default enabled.
static const struct ldma_inst_data dma1tx = {
	...
	.desc_fod = true;
	.desc_in_sram = true;
};

In the SW descriptor management case,  the device tree would be like:

dma1tx: dma-controller@e7300000 {
      compatible = "intel,lgm-dma1tx";
      reg = <0xe7300000 0x1000>;
      ...
      #dma-cells = <3>;
      intel,dma-poll-cnt = <16>;
      intel,dma-sw-desc;
};

eth: eth@a00000 {
   dmas = <&dma1tx 0 0 64>;
};
Ethernet driver is an example to use the DMA to transfer data.  
In the SW descriptor management case,  DMA driver must turn off
DMA HW feature desc_fod and desc_in_sram to give the control to CPU.

Best regards,
Yixin