Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Greg KH]

On Tue, Aug 19, 2025 at 12:39:02AM +0200, Pavel Pisa wrote:
> Hello Greg and others,
> 
> please, is there some progress/decision about the fix for mainline?
> 
> Our daily test of mainline Linux kernel build and test of CAN
> communication latency on Zynq system with loaded CTU CAN FD
> IP core ends with unresponsive kernel. The last successful
> mainline build is from July 29
>  
>   run-250729-042256-hist+6.16.0-g283564a43383+oaat-kern.json
>   https://canbus.pages.fel.cvut.cz/can-latester/
> 
> I have analyzed the cause and reported (August 4) that mainline
> Zynq runtime FPGA bitstream loading was broken by patch
> 
>   37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> 
> Xu Yilun and others from the FPGA community reacted promptly
> with the fix on August 6. The fix has propagated into linux-next.
> Is there a plan to accept it for the 6.17 version, or would it be
> accepted only for 6.18?

It's in my "to apply" queue to get to for 6.17-final.

Please give us a chance to catch up, August is usually a time for
vacations :)

thanks,

greg k-h