[PATCH v2 3/3] riscv: dts: thead: Scope the reset controller to VO for TH1520

[Yao Zi]

The only reset-controller described in TH1520's SoC devicetree takes
control of reset signals in VO subsystem, while using a generic
"thead,th1520-reset" compatible that may imply control over the whole
SoC.

To avoid such confusion, let's replace the compatible with the new
introduced "thead,th1520-reset-vo" that explicitly describes the
controller's scope. The controller's label is updated as well.

Fixes: 1b136de08b5f ("riscv: dts: thead: Introduce reset controller node")
Reported-by: Icenowy Zheng <uwu@xxxxxxxxxx>
Co-developed-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx>
Signed-off-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx>
Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 03f1d7319049..025402f6aa21 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -235,7 +235,7 @@ aon: aon {
 		compatible = "thead,th1520-aon";
 		mboxes = <&mbox_910t 1>;
 		mbox-names = "aon";
-		resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>;
+		resets = <&rst_vo TH1520_RESET_ID_GPU_CLKGEN>;
 		reset-names = "gpu-clkgen";
 		#power-domain-cells = <1>;
 	};
@@ -502,8 +502,8 @@ clk: clock-controller@ffef010000 {
 			#clock-cells = <1>;
 		};
 
-		rst: reset-controller@ffef528000 {
-			compatible = "thead,th1520-reset";
+		rst_vo: reset-controller@ffef528000 {
+			compatible = "thead,th1520-reset-vo";
 			reg = <0xff 0xef528000 0x0 0x4f>;
 			#reset-cells = <1>;
 		};
-- 
2.50.1