RE: [PATCH v8 03/15] PCI: cadence: Add register definitions for High Perf Architecture (HPA)

[Manikandan Karunakaran Pillai]

>
>
>
>On 8/19/2025 5:22 PM, hans.zhang@xxxxxxxxxxx wrote:
>> +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar)                \
>> +		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) *
>10))
>> +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar)               \
>> +		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) *
>10))
>> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar)              \
>> +		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar)
>* 10))
>> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
>> +
>	(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS <<
>((bar) * 10))
>> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar)              \
>> +		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar)
>* 10))
>> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
>> +
>	(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS <<
>((bar) * 10))
>> +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture)           \
>> +		(((aperture) - 7) << ((bar) * 10))
>> +
>> +#define CDNS_PCIE_HPA_LM_PTM_CTRL		0x0520
>> +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN	BIT(17)
>
>Is that TPM intentional or a typo?
>

Thanks Alok for your comments. It is not intentional but it was copied from an earlier available code 
and is used across HPA and Legacy code. I will submit a bug fix patch later for fixing this issue. 

>Thanks,
>Alok