RE: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[Hal Feng]

> -----Original Message-----
> From: E Shattow <e@xxxxxxxxxxxx>
> Sent: 2025年8月20日 11:49
> To: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>; Conor Dooley <conor@xxxxxxxxxx>;
> Emil Renner Berthing <kernel@xxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>;
> Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Paul Walmsley
> <paul.walmsley@xxxxxxxxxx>; Palmer Dabbelt <palmer@xxxxxxxxxxx>; Albert
> Ou <aou@xxxxxxxxxxxxxxxxx>; Alexandre Ghiti <alex@xxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-
> riscv@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram
> hinting needed by boot loader
> 
> 
> 
> On 8/17/25 23:05, Hal Feng wrote:
> >> On 15.08.25 15:37, E Shattow wrote:
> >> Add bootph-pre-ram hinting to jh7110.dtsi:
> >>   - CPU interrupt controller(s)
> >>   - core local interrupt timer
> >>   - DDR memory controller
> >>   - oscillator
> >>   - syscrg clock-controller
> >>
> >> Signed-off-by: E Shattow <e@xxxxxxxxxxxx>
> >> ---
> >>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
> >>  1 file changed, 9 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> index 14df3d062a45..884a3526cb0f 100644
> >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
> >>
> >>  			cpu0_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
> >>
> >>  			cpu1_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
> >>
> >>  			cpu2_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
> >>
> >>  			cpu3_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
> >>
> >>  			cpu4_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
> >>
> >>  	osc: oscillator {
> >>  		compatible = "fixed-clock";
> >> +		bootph-pre-ram;
> >>  		clock-output-names = "osc";
> >>  		#clock-cells = <0>;
> >>  	};
> >> @@ -354,6 +360,7 @@ soc {
> >>  		clint: timer@2000000 {
> >>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
> >>  			reg = <0x0 0x2000000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
> >> 7>,
> >>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> >>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> @@ -376,6 +383,7 @@
> >> memory-controller@15700000 {
> >>  			compatible = "starfive,jh7110-dmc";
> >>  			reg = <0x0 0x15700000 0x0 0x10000>,
> >>  			      <0x0 0x13000000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> >>  			clock-names = "pll1_out";
> >>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -
> >> 892,6 +900,7 @@ qspi: spi@13010000 {
> >>  		syscrg: clock-controller@13020000 {
> >>  			compatible = "starfive,jh7110-syscrg";
> >>  			reg = <0x0 0x13020000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			clocks = <&osc>, <&gmac1_rmii_refin>,
> >>  				 <&gmac1_rgmii_rxin>,
> >>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> >
> > pllclk also needs to add bootph-pre-ram. Because it is the dependency of
> syscrg.
> >
> > 		pllclk: clock-controller {
> > 			compatible = "starfive,jh7110-pll";
> > +			bootph-pre-ram;
> > 			clocks = <&osc>;
> > 			#clock-cells = <1>;
> > 		};
> >
> > Best regards,
> > Hal
> 
> What users are there for 'pllclk' at U-Boot SPL phase? There does not seem to
> be any difference in testing U-Boot and Linux with or without this hint for
> 'pllclk'.

I see commit 8b3f2eb7d8912204bda2d914b8a9a1ce1c31bb5c adding this line to
solve some problems.

https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schuchardt@xxxxxxxxxxxxx/

Best regards,
Hal