Re: [PATCH net-next v2 4/6] net: dsa: lantiq_gswip: support offset of MII registers

[Hauke Mehrtens]

On 8/27/25 01:06, Daniel Golle wrote:
> The MaxLinear GSW1xx family got a single (R)(G)MII port at index 5 but
> the registers MII_PCDU and MII_CFG are those of port 0.
> Allow applying an offset for the port index to access those registers.
>
> Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
> ---
> v2: no changes
>
>   drivers/net/dsa/lantiq/lantiq_gswip.c | 12 ++++++++++--
>   drivers/net/dsa/lantiq/lantiq_gswip.h |  1 +
>   2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq/lantiq_gswip.c
> index 3e2a54569828..64e378852284 100644
> --- a/drivers/net/dsa/lantiq/lantiq_gswip.c
> +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c
....
> diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h
> index 19bbe6fddf04..2df9c8e8cfd0 100644
> --- a/drivers/net/dsa/lantiq/lantiq_gswip.h
> +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h
> @@ -233,6 +233,7 @@ struct gswip_hw_info {
>   	int max_ports;
>   	unsigned int allowed_cpu_ports;
>   	unsigned int mii_ports;
> +	int mii_port_reg_offset;

Maybe you should set the mii_port_reg_offset attribute explicitly to 0.

>   	const struct gswip_pce_microcode (*pce_microcode)[];
>   	size_t pce_microcode_size;
>   	enum dsa_tag_protocol tag_protocol;

Hauke