Re: [PATCH 09/15] iio: adc: ad4030: Support multiple data lanes per channel

[Andy Shevchenko]

On Sat, Aug 30, 2025 at 3:43 AM Marcelo Schmitt
<marcelo.schmitt@xxxxxxxxxx> wrote:
>
> AD4030 and similar chips can output ADC sample data through 1, 2, or 4
> lines per channel. The number of SPI lines the device uses to output data
> is specified in firmware. Parse SPI read bus width setting from firmware
> and configure the device to use that amount of lines to output data.

...

> -               offload_bpw  = data_width;
> +               offload_bpw  = data_width / (1 << st->lane_mode);

This is interesting. What's the difference you see to the use of the
right shift?
Also note, in case of lane_mode == 31 (yeah, I understand that here
it's not the case) this is UB in accordance with C standard.

-- 
With Best Regards,
Andy Shevchenko