Re: [PATCH v7] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared

From: Dmitry Baryshkov
Date: Tue Sep 09 2025 - 10:23:24 EST


On Mon, Sep 08, 2025 at 11:49:51AM +0200, Krzysztof Kozlowski wrote:
> Hardware Programming Guide for DSI PHY says that PLL_SHUTDOWNB and
> DIGTOP_PWRDN_B have to be asserted for any PLL register access.
> Whenever dsi_pll_7nm_vco_recalc_rate() or dsi_pll_7nm_vco_set_rate()
> were called on unprepared PLL, driver read values of zero leading to all
> sort of further troubles, like failing to set pixel and byte clock
> rates.
>
> Asserting the PLL shutdown bit is done by dsi_pll_enable_pll_bias() (and
> corresponding dsi_pll_disable_pll_bias()) which are called through the
> code, including from PLL .prepare() and .unprepare() callbacks.
>
> The .set_rate() and .recalc_rate() can be called almost anytime from
> external users including times when PLL is or is not prepared, thus
> driver should not interfere with the prepare status.
>
> Implement simple reference counting for the PLL bias, so
> set_rate/recalc_rate will not change the status of prepared PLL.
>
> Issue of reading 0 in .recalc_rate() did not show up on existing
> devices, but only after re-ordering the code for SM8750.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>
> ---
>
> Continuing changelog from "drm/msm: Add support for SM8750" where this
> was part of.
>
> Changes in v7:
> - Rebase
> - I did not remove ndelay(250) as discussed with Dmitry, because:
> 1. Indeed the HPG does not mention any delay needed, unlike PHY 10 nm.
> 2. However downstream source code for PHY 3+4+5 nm has exactly these
> delays. This could be copy-paste or could be intentional workaround
> for some issue about which I have no clue. Timings are tricky and
> I don't think I should be introducing changes without actually
> knowing them.
> - Add Rb tags
> - Link to v6: https://lore.kernel.org/r/20250610-b4-sm8750-display-v6-0-ee633e3ddbff@xxxxxxxxxx
>
> Changes in v6:
> 1. Print error on pll bias enable/disable imbalance refcnt
>
> Changes in v5:
> 1. New patch
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 53 +++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>


--
With best wishes
Dmitry