Re: [PATCH v5 0/4] clk: tegra: add DFLL support for Tegra114

[Thierry Reding]

On Mon, Sep 01, 2025 at 04:57:37PM +0200, Thierry Reding wrote:
> On Fri, Aug 29, 2025 at 03:22:30PM +0300, Svyatoslav Ryhel wrote:
> > DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on
> > a ring oscillator and translates voltage changes into frequency
> > compensation changes needed to prevent the CPU from failing and is
> > essential for correct CPU frequency scaling.
> > 
> > ---
> > Changes in v2:
> > - dropped 'drivers:' from commit title
> > - aligned naming to Tegra114
> > 
> > Changes in v3:
> > - add DFLL support for Tegra 114 was split into dt header addition,
> >   DFLL reset configuration and CVB tables implementation.
> > - added cleaner commit message to dt header commit
> > - added T210_ prefixes to Tegra210 CVB table macros
> > 
> > Changes in v4:
> > - expanded commit message of car header adding commit
> > 
> > Changes in v5:
> > - renamed tegra114-car.h to nvidia,tegra114-car.h
> > ---
> > 
> > Svyatoslav Ryhel (4):
> >   dt-bindings: reset: add Tegra114 car header
> >   clk: tegra: add DFLL DVCO reset control for Tegra114
> >   clk: tegra: dfll: add CVB tables for Tegra114
> >   ARM: tegra: Add DFLL clock support for Tegra114
> 
> Hi Michael, Stephen,
> 
> Given the cross-dependency between the dt-bindings header, the driver
> and the DT, do you want me to pick this up into the Tegra tree and
> resolve the dependency there?

I've applied these four patches to the Tegra tree now and plan to send
the drivers/clk bits to you as a pull request. Let me know if you have
any objections.

Thanks,
Thierry

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