Re: [PATCH v2 1/4] clk: tegra20: reparent dsi clock to pll_d_out0
From: Stephen Boyd
Date: Sun Sep 21 2025 - 16:08:08 EST
Quoting Svyatoslav Ryhel (2025-09-06 06:16:52)
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
> ---
Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>