Re: [PATCH v4 6/8] clk: loongson2: Add clock definitions for Loongson-2K0300 SoC

[Stephen Boyd]

Quoting Yao Zi (2025-09-19 07:26:47)
> The clock controller of Loongson-2K0300 consists of three PLLs, requires
> an 120MHz external reference clock to function, and generates clocks in
> various frequencies for SoC peripherals.
> 
> Clock definitions for previous SoC generations could be reused for most
> clock hardwares. There're two gates marked as critical, clk_node_gate
> and clk_boot_gate, which supply the CPU cores and the system
> configuration bus. Disabling them leads to a SoC hang.
> 
> Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
> ---

Applied to clk-next