[PATCH RESEND v6 0/2] riscv: Use GCR.U timer device as clocksource
From: Aleksa Paunovic via B4 Relay
Date: Wed Sep 24 2025 - 07:11:23 EST
This series adds bindings for the GCR.U timer device and corresponding
driver support. Accessing the memory mapped mtime register in the GCR.U
region should be faster than trapping to M mode each time the timer
needs to be read.
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx>
---
Changes in v6:
- Rename mti,gcru to mips,p8700-gcru
- Link to v5: https://lore.kernel.org/r/20250711-riscv-time-mmio-v5-0-9ed1f825ad5e@xxxxxxxxxxxxx
Changes in v5:
- Fixed build issues on 32-bit RISC-V and sparse warnings
- Remove clint_time_val and clint.h, replace with riscv_time_val
- Depend on RISCV_TIMER in Kconfig
Changes in v4:
- Remove "select" from mti,gcru.yaml.
- Refactor the driver to use function pointers instead of static keys.
Previous versions:
v1: https://lore.kernel.org/lkml/20241227150056.191794-1-arikalo@xxxxxxxxx/#t
v2: https://lore.kernel.org/linux-riscv/20250409143816.15802-1-aleksa.paunovic@xxxxxxxxxxxxx/
v3: https://lore.kernel.org/linux-riscv/DU0PR09MB61968695A2A3146EE83B7708F6BA2@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
v4: https://lore.kernel.org/r/20250514-riscv-time-mmio-v4-0-cb0cf2922d66@xxxxxxxxxxxxx
v5: https://lore.kernel.org/r/20250711-riscv-time-mmio-v5-0-9ed1f825ad5e@xxxxxxxxxxxxx
---
Aleksa Paunovic (2):
dt-bindings: timer: mips,p8700-gcru
riscv: Allow for riscv-clock to pick up mmio address.
.../devicetree/bindings/timer/mips,p8700-gcru.yaml | 38 +++++++++++++
arch/riscv/include/asm/clint.h | 26 ---------
arch/riscv/include/asm/timex.h | 63 ++++++++++++----------
drivers/clocksource/Kconfig | 12 +++++
drivers/clocksource/timer-clint.c | 20 ++++---
drivers/clocksource/timer-riscv.c | 34 ++++++++++++
6 files changed, 128 insertions(+), 65 deletions(-)
---
base-commit: 038d61fd642278bab63ee8ef722c50d10ab01e8f
change-id: 20250424-riscv-time-mmio-5628e0fca8af
Best regards,
--
Aleksa Paunovic <aleksa.paunovic@xxxxxxxxxxxxx>