[PATCH v2 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling

From: Pankaj Patil
Date: Thu Sep 25 2025 - 02:31:02 EST

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From: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>

Add sram and scmi nodes required to have a functional cpu dvfs
on Glymur SoCs.

Signed-off-by: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxx>
Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 87 +++++++++++++++++++++---------------
1 file changed, 51 insertions(+), 36 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index ae013c64e096b7c90c0aa4cfc50f078a85518acb..d924b4778fd37af8fe7b0bceca466dee73269481 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -46,8 +46,8 @@ cpu0: cpu0@0 {
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
- power-domains = <&CPU_PD0>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD0>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;

@@ -63,8 +63,8 @@ cpu1: cpu1@100 {
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
- power-domains = <&CPU_PD1>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD1>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -74,8 +74,8 @@ cpu2: cpu2@200 {
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
- power-domains = <&CPU_PD2>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD2>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -85,8 +85,8 @@ cpu3: cpu3@300 {
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
- power-domains = <&CPU_PD3>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD3>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -96,8 +96,8 @@ cpu4: cpu4@400 {
compatible = "qcom,oryon";
reg = <0x0 0x400>;
enable-method = "psci";
- power-domains = <&CPU_PD4>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD4>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -107,8 +107,8 @@ cpu5: cpu5@500 {
compatible = "qcom,oryon";
reg = <0x0 0x500>;
enable-method = "psci";
- power-domains = <&CPU_PD5>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD5>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -118,8 +118,8 @@ cpu6: cpu6@10000 {
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
- power-domains = <&CPU_PD6>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD6>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;

@@ -135,8 +135,8 @@ cpu7: cpu7@10100 {
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
- power-domains = <&CPU_PD7>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD7>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -146,8 +146,8 @@ cpu8: cpu8@10200 {
compatible = "qcom,oryon";
reg = <0x0 0x10200>;
enable-method = "psci";
- power-domains = <&CPU_PD8>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD8>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -157,8 +157,8 @@ cpu9: cpu9@10300 {
compatible = "qcom,oryon";
reg = <0x0 0x10300>;
enable-method = "psci";
- power-domains = <&CPU_PD9>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD9>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -168,8 +168,8 @@ cpu10: cpu10@10400 {
compatible = "qcom,oryon";
reg = <0x0 0x10400>;
enable-method = "psci";
- power-domains = <&CPU_PD10>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD10>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -179,8 +179,8 @@ cpu11: cpu11@10500 {
compatible = "qcom,oryon";
reg = <0x0 0x10500>;
enable-method = "psci";
- power-domains = <&CPU_PD11>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD11>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -190,8 +190,8 @@ cpu12: cpu12@20000 {
compatible = "qcom,oryon";
reg = <0x0 0x20000>;
enable-method = "psci";
- power-domains = <&CPU_PD12>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD12>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;

@@ -207,8 +207,8 @@ cpu13: cpu13@20100 {
compatible = "qcom,oryon";
reg = <0x0 0x20100>;
enable-method = "psci";
- power-domains = <&CPU_PD13>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD13>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -218,8 +218,8 @@ cpu14: cpu14@20200 {
compatible = "qcom,oryon";
reg = <0x0 0x20200>;
enable-method = "psci";
- power-domains = <&CPU_PD14>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD14>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -229,8 +229,8 @@ cpu15: cpu15@20300 {
compatible = "qcom,oryon";
reg = <0x0 0x20300>;
enable-method = "psci";
- power-domains = <&CPU_PD15>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD15>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -240,8 +240,8 @@ cpu16: cpu16@20400 {
compatible = "qcom,oryon";
reg = <0x0 0x20400>;
enable-method = "psci";
- power-domains = <&CPU_PD16>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD16>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -251,8 +251,8 @@ cpu17: cpu17@20500 {
compatible = "qcom,oryon";
reg = <0x0 0x20500>;
enable-method = "psci";
- power-domains = <&CPU_PD17>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD17>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -397,6 +397,21 @@ scm: scm {
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+ };
};

reserved-memory {

--
2.34.1

Next message: Pankaj Patil: "[PATCH v2 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes"
Previous message: Pankaj Patil: "[PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines"
In reply to: Dmitry Baryshkov: "Re: [PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines"
Next in thread: Pankaj Patil: "[PATCH v2 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes"
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