Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5

[Konrad Dybcio]

On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@xxxxxxxxxxx>
> 
> Describe PCIe5 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe5.
> 
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@xxxxxxxxxxx>
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
> ---

[...]

> +		pcie5: pci@1b40000 {
> +			device_type = "pci";
> +			compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> +			reg = <0x0 0x01b40000 0x0 0x3000>,
> +			      <0x7 0xa0000000 0x0 0xf20>,
> +			      <0x7 0xa0000f40 0x0 0xa8>,
> +			      <0x7 0xb0000000 0x0 0x4000>,
> +			      <0x7 0xa0100000 0x0 0x100000>,
> +			      <0x0 0x01b43000 0x0 0x1000>;
> +			reg-names = "parf",
> +				    "dbi",
> +				    "elbi",
> +				    "atu",
> +				    "config",
> +				    "mhi";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			ranges = <0x02000000 0 0x7a000000 0 0x7a000000 0 0x4000000>;

No I/O space? We can also add the (presumably prefetchable) 64-bit range 


> +			pcie5port0: pcie@0 {

pcie5_port0:

> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +				phys = <&pcie5_phy>;

same comment as on the other patch

Konrad