[PATCH 1/4] dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper

[adrianhoyin . ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@xxxxxxxxxx>

Add a device tree binding document for the Altera wrapper around the
Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
SoC-specific integration such as clock and reset control for the USB
subsystem.

A parent–child node structure is used to comply with the generic DWC3
binding, which restricts the core node to a single clock and reset.
The wrapper node provides the additional clocks, resets, and address
translation required for the Agilex5 integration.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@xxxxxxxxxx>
---
 .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml

diff --git a/Documentation/devicetree/bindings/usb/dwc3-altera.yaml b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
new file mode 100644
index 000000000000..c998d587723d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/dwc3-altera.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera DWC3 USB Controller Wrapper
+
+maintainers:
+  - Adrian Ng <adrianhoyin.ng@xxxxxxxxxx>
+
+description: |
+  The Altera SoCFPGA wrapper around the Synopsys DesignWare USB3 (DWC3) core.
+  The wrapper provides SoC-specific integration such as reset and clock control.
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+required:
+  - compatible
+  - reg
+  - ranges
+  - clocks
+  - resets
+
+patternProperties:
+  "^usb(@[0-9a-f]+)?$":
+    type: object
+    $ref: /schemas/usb/snps,dwc3.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    usb@11000000 {
+        compatible = "altr,agilex5-dwc3";
+        reg = <0x11000000 0x100000>;
+        ranges = <0x0 0x11000000 0x100000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        clocks = <&clkmgr 54>, <&clkmgr 55>;
+        resets = <&rst 36>, <&rst 44>;
+
+        dwc3: usb@0 {
+            compatible = "snps,dwc3";
+            reg = <0x0 0x100000>;
+            interrupts = <0 94 4>;
+            iommus = <&smmu 7>;
+            phys = <&usbphy0>, <&usbphy0>;
+            phy-names = "usb2-phy", "usb3-phy";
+            dr_mode = "host";
+            maximum-speed = "super-speed";
+            snps,dis_u2_susphy_quirk;
+            snps,dis_u3_susphy_quirk;
+            status = "okay";
+        };
+    };
+...
-- 
2.49.GIT