Re: [PATCH v2] EDAC/altera: Handle OCRAM ECC enable after warm reset

[Borislav Petkov]

On Tue, Nov 11, 2025 at 04:08:01PM +0800, niravkumarlaxmidas.rabara@xxxxxxxxxx wrote:
> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@xxxxxxxxxx>
> 
> The OCRAM ECC is always enabled either by the BootROM or by the Secure
> Device Manager (SDM) during a power-on reset on SoCFPGA.
> 
> However, during a warm reset, the OCRAM content is retained to preserve
> data, while the control and status registers are reset to their default
> values. As a result, ECC must be explicitly re-enabled after a warm reset.
> 
> Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@xxxxxxxxxx>
> Acked-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
> 
> v2 changes:
>  - Add Fixes and Cc tags
>  - Retains Acked-by from v1 patch
> 
> v1 link:
> https://lore.kernel.org/all/20251103140920.1060643-1-niravkumarlaxmidas.rabara@xxxxxxxxxx/
> 
>  drivers/edac/altera_edac.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

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