Re: [PATCH 6/7] clk: thead: th1520-ap: Support CPU frequency scaling

[Drew Fustini]

On Thu, Nov 20, 2025 at 01:14:15PM +0000, Yao Zi wrote:
> On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly
> reparented to one of the two PLLs: either to cpu_pll0 indirectly through
> c910_i0_clk, or to cpu_pll1 directly.
> 
> To achieve glitchless rate change, customized clock operations are
> implemented for c910_clk: on rate change, the PLL not currently in use
> is configured to the requested rate first, then c910_clk reparents to
> it.
> 
> Additionally, c910_bus_clk, which in turn takes c910_clk as parent,
> has a frequency limit of 750MHz. A clock notifier is registered on
> c910_clk to adjust c910_bus_clk on c910_clk rate change.
> 
> Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
> ---
>  drivers/clk/thead/clk-th1520-ap.c | 148 +++++++++++++++++++++++++++++-
>  1 file changed, 146 insertions(+), 2 deletions(-)
[...] 
> +/*
> + * c910_clk could be reparented glitchlessly for DVFS. There are two parents,
> + *  - c910_i0_clk, dervided from cpu_pll0_clk or osc_24m.

Typo: 'derived' instead of 'dervided'.

[...]

Unless there are other comments that require changes, I can fix up the
typo when applied.

Reviewed-by: Drew Fustini <fustini@xxxxxxxxxx>