Re: [PATCH 2/2] x86/resctrl: Fix memory bandwidth counter width for Hygon

[Reinette Chatre]

Hi Xiaochen,

On 12/4/25 6:38 PM, Xiaochen Shen wrote:
> Hi Tony,
> 
> On 12/5/2025 1:11 AM, Luck, Tony wrote:
>> I *think* you'd get the right results if the h/w counter is wider
>> than s/w expects. You'd just need to keep polling fast enough
>> (and we never adjusted the MBM polling rate from the original
>> 1 HZ.)
> 
> Thank you very much for code review!
> 
> We have observed a test case where an incorrect counter width leads to random unexpected memory bandwidth readings:
> https://github.com/shenxiaochen/my_documents/blob/main/memory_bandwidth_counter_width_and_overflow_issue_steps_to_reproduce.txt

Could this perhaps be related to issue fixed by:
15292f1b4c55 ("x86/resctrl: Fix miscount of bandwidth event when reactivating previously unavailable RMID")?

Reinette