[PATCH V2 1/3] dt-bindings: watchdog: Add support for Andes ATCWDT200
From: CL Wang
Date: Thu Jan 15 2026 - 03:15:27 EST
Add the devicetree binding documentation for the Andes ATCWDT200
watchdog timer.
ATCWDT200 is the IP name, which is embedded in AndesCore-based
platforms or SoCs such as AE350 and Qilai.
Signed-off-by: CL Wang <cl634@xxxxxxxxxxxxx>
---
Changes in v2:
- Drop redundant text "including supported properties..." from the
commit message.
- Clarify the relationship between ATCWDT200 IP and SoCs (AE350/Qilai)
in the commit message.
- Add missing type definition ($ref: uint32), enum constraint, and
description for 'andestech,clock-source' property.
---
.../watchdog/andestech,ae350-wdt.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
diff --git a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
new file mode 100644
index 000000000000..f1107c552788
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/andestech,ae350-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes ATCWDT200 Watchdog Timer
+
+maintainers:
+ - CL Wang <cl634@xxxxxxxxxxxxx>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - andestech,qilai-wdt
+ - const: andestech,ae350-wdt
+ - const: andestech,ae350-wdt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ andestech,clock-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description: |
+ Select the clock source for the watchdog timer.
+ 0 - External clock
+ 1 - P clock
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - andestech,clock-source
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@f0500000 {
+ compatible = "andestech,ae350-wdt";
+ reg = <0xf0500000 0x20>;
+ clocks = <&clk_wdt>;
+ andestech,clock-source = <0>;
+ };
--
2.34.1