Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support

[Lad, Prabhakar]

Hi Thomas,

On Thu, Jan 29, 2026 at 9:59 PM Thomas Gleixner <tglx@xxxxxxxxxx> wrote:
>
> On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
> > On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@xxxxxxxxxx> wrote:
> >>
> >> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> >> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >> >
> >> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> >> > that allows software to explicitly assert interrupts toward individual
> >> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> >> > interrupt.
> >> >
> >> > Introduce a debug mechanism to trigger software interrupts on individual
> >> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> >> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> >> > explicitly enabled.
> >>
> >> Can't you reuse/extend the existing mechanism provided by
> >> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
> >> instead of implementing yet another ad hoc debugfs magic?
> >>
> > Can you please point me to a driver which makes use of it? In my case
> > the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
> > ICU_SWINT.
>
> Care to look what irq_inject_interrupt() does?
>
> It tries first to inject the interrupt via irq_set_irqchip_state(),
> which only works when a chip in the hierarchy implements the
> chip::irq_set_irqchip_state() callback.
>
I did implement irq_set_irqchip_state but it doesn't land in the
rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed
something.

#Trigger int-ca55-0
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14

#The trace looks like below:
irq_debug_write()
  -> irq_inject_interrupt()
     -> irq_set_irqchip_state()

This lands in GICV3. For the RZ/V2H ICU only interrupts port_irqx and
tintx interrupts are registered  in irq_domain_create_hierarchy() for
the rest of the interrupts these are supposed to be directly handled
by GICv3.

root@rzv2h-evk:/sys/kernel/debug/irq/irqs# cat /proc/interrupts | grep
interr | grep 294
 14:          1          0          0          0    GICv3 294 Edge
 10400000.interrupt-controller
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# cat 14
handler:  handle_fasteoi_irq
device:   (null)
status:   0x00000001
istate:   0x00004000
ddepth:   0
wdepth:   0
dstate:   0x0b400201
            IRQ_TYPE_EDGE_RISING
            IRQD_ACTIVATED
            IRQD_IRQ_STARTED
            IRQD_SINGLE_TARGET
            IRQD_DEFAULT_TRIGGER_SET
            IRQD_HANDLE_ENFORCE_IRQCTX
node:     -1
affinity: 0-3
effectiv: 0
domain:  :soc:interrupt-controller@14900000-1
 hwirq:   0x126
 chip:    GICv3
  flags:   0x15
             IRQCHIP_SET_TYPE_MASKED
             IRQCHIP_MASK_ON_SUSPEND
             IRQCHIP_SKIP_SET_WAKE

How do you propose to handle this? irq_inject_interrupt() would work
if I move int-ca55-x and icu-error-ca55 under
irq_domain_create_hierarchy().

Cheers,
Prabhakar