RE: [PATCH v2 3/3] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support

[Hongxing Zhu]

> -----Original Message-----
> From: Sherry Sun <sherry.sun@xxxxxxx>
> Sent: 2026年2月9日 14:59
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>; Frank Li <frank.li@xxxxxxx>;
> robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; festevam@xxxxxxxxx
> Cc: kernel@xxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: RE: [PATCH v2 3/3] arm64: dts: imx943-evk: Add pcie[0,1] and
> pcie-ep[0,1] support
> 
> > Subject: [PATCH v2 3/3] arm64: dts: imx943-evk: Add pcie[0,1] and
> > pcie- ep[0,1] support
> >
> > Add pcie[0,1] and pcie-ep[0,1] support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> >  arch/arm64/boot/dts/freescale/imx943-evk.dts | 82
> > ++++++++++++++++++++
> >  1 file changed, 82 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > index 765d9d05e489d..524bcb5951151 100644
> > --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> > @@ -49,6 +49,20 @@ chosen {
> >  		stdout-path = &lpuart1;
> >  	};
> >
> > +	pcie_ref_clk: clock-pcie-ref {
> > +		compatible = "gpio-gate-clock";
> > +		clocks = <&xtal25m>;
> > +		#clock-cells = <0>;
> > +		enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>;
> > +	};
> > +
> > +	xtal25m: clock-xtal25m {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <25000000>;
> > +		clock-output-names = "xtal_25MHz";
> > +	};
> > +
> >  	dmic: dmic {
> >  		compatible = "dmic-codec";
> >  		#sound-dai-cells = <0>;
> > @@ -70,6 +84,15 @@ reg_m2_pwr: regulator-m2-pwr {
> >  		startup-delay-us = <5000>;
> >  	};
> >
> > +	reg_slot_pwr: regulator-slot-pwr {
> > +		compatible = "regulator-fixed";
> > +		regulator-name = "PCIe slot-power";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>;
> > +		enable-active-high;
> > +	};
> > +
> >  	reg_m2_wlan: regulator-wlan {
> >  		compatible = "regulator-fixed";
> >  		regulator-name = "WLAN_EN";
> > @@ -641,6 +664,18 @@ IMX94_PAD_GPIO_IO28__LPI2C6_SCL
> > 	0x40000b9e
> >  		>;
> >  	};
> >
> > +	pinctrl_pcie0: pcie0grp {
> > +		fsl,pins = <
> > +			IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B
> > 	0x4000031e
> > +		>;
> > +	};
> > +
> > +	pinctrl_pcie1: pcie1grp {
> > +		fsl,pins = <
> > +			IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B
> > 	0x4000031e
> > +		>;
> > +	};
> > +
> >  	pinctrl_pdm: pdmgrp {
> >  		fsl,pins = <
> >  			IMX94_PAD_PDM_CLK__PDM_CLK
> > 	0x31e
> > @@ -800,6 +835,53 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS	0x3fe
> >  	};
> >  };
> >
> > +&pcie0 {
> > +	pinctrl-0 = <&pinctrl_pcie0>;
> > +	pinctrl-names = "default";
> > +	clocks = <&scmi_clk IMX94_CLK_HSIO>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPLL>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>,
> > +		 <&pcie_ref_clk>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
> > +		      "ref", "extref";
> > +	reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
> > +	vpcie3v3aux-supply = <&reg_m2_wlan>;
> 
> Missing vpcie-supply?
> 
> > +	supports-clkreq;
> > +	status = "okay";
> > +};
> > +
> > +&pcie0_ep {
> > +	pinctrl-0 = <&pinctrl_pcie0>;
> > +	pinctrl-names = "default";
> > +	vpcie3v3aux-supply = <&reg_m2_wlan>;
> > +	status = "disabled";
> > +};
> > +
> > +&pcie1 {
> > +	pinctrl-0 = <&pinctrl_pcie1>;
> > +	pinctrl-names = "default";
> > +	clocks = <&scmi_clk IMX94_CLK_HSIO>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPLL>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
> > +		 <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
> > +		 <&hsio_blk_ctl 0>,
> > +		 <&pcie_ref_clk>;
> > +	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
> > +		      "ref", "extref";
> > +	reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
> > +	vpcie3v3aux-supply = <&reg_slot_pwr>;
> 
> Same here.
It's not required anymore. Since the port power is enabled by
 vpcie3v3aux-supply already.

Best Regards
Richard Zhu
> 
> Best Regards
> Sherry
> 
> 
> > +	status = "okay";
> > +};
> > +
> > +&pcie1_ep {
> > +	pinctrl-0 = <&pinctrl_pcie1>;
> > +	pinctrl-names = "default";
> > +	vpcie3v3aux-supply = <&reg_slot_pwr>;
> > +	status = "disabled";
> > +};
> > +
> >  &usdhc1 {
> >  	pinctrl-0 = <&pinctrl_usdhc1>;
> >  	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > --
> > 2.37.1