Re: [PATCH 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths

[Neil Armstrong]

On 2/8/26 02:28, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@xxxxxxxxx>
>
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
>
> Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 308 +++++++++++++++++++++++++++++++++++
>   1 file changed, 308 insertions(+)
<snip>

Tested on an SM8550-HDK with mybw and sysbench, similar values reported
in performance governor on all CPU clusters.

Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8550-HDK