Re: [RFC PATCH 3/3] PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)
From: Ilpo Järvinen
Date: Wed Feb 18 2026 - 16:09:15 EST
On Tue, 17 Feb 2026, Ionut Nechita (Sunlight Linux) wrote:
The subject should start with
PCI/bwctrl:
...and you then don't need to repeat bandwidth control anymore.
> From: Ionut Nechita <ionut_n2001@xxxxxxxxx>
>
> Update PCIe subsystem components to support 128 GT/s link speed:
>
> - bwctrl: Extend pcie_valid_speed() range to PCIE_SPEED_128_0GT,
> add PCIE_SPEED_128_0GT to speed conversion table, widen
> supported_speeds variables from u8 to u16
> - portdrv: Switch hweight8() to hweight16() for supported_speeds
> to match the widened type
> - pcie_cooling: Add static_assert for PCIE_SPEED_128_0GT enum
> contiguity check
>
> Signed-off-by: Ionut Nechita <ionut_n2001@xxxxxxxxx>
> ---
> drivers/pci/pcie/bwctrl.c | 7 ++++---
> drivers/pci/pcie/portdrv.c | 2 +-
> drivers/thermal/pcie_cooling.c | 1 +
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> index 36f939f23d34e..b9125b40cb860 100644
> --- a/drivers/pci/pcie/bwctrl.c
> +++ b/drivers/pci/pcie/bwctrl.c
> @@ -50,7 +50,7 @@ static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>
> static bool pcie_valid_speed(enum pci_bus_speed speed)
> {
> - return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> + return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_128_0GT);
> }
>
> static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> @@ -62,6 +62,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> [PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
> [PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
> [PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
> + [PCIE_SPEED_128_0GT] = PCI_EXP_LNKCTL2_TLS_128_0GT,
> };
>
> if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
> @@ -70,7 +71,7 @@ static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> return speed_conv[speed];
> }
>
> -static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
> +static inline u16 pcie_supported_speeds2target_speed(u16 supported_speeds)
> {
> return __fls(supported_speeds);
> }
> @@ -88,7 +89,7 @@ static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
> static u16 pcie_bwctrl_select_speed(struct pci_dev *port, enum pci_bus_speed speed_req)
> {
> struct pci_bus *bus = port->subordinate;
> - u8 desired_speeds, supported_speeds;
> + u16 desired_speeds, supported_speeds;
> struct pci_dev *dev;
>
> desired_speeds = GENMASK(pci_bus_speed2lnkctl2(speed_req),
> diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
> index 38a41ccf79b9a..5ee8795107f26 100644
> --- a/drivers/pci/pcie/portdrv.c
> +++ b/drivers/pci/pcie/portdrv.c
> @@ -274,7 +274,7 @@ static int get_port_device_capability(struct pci_dev *dev)
>
> pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &linkcap);
> if (linkcap & PCI_EXP_LNKCAP_LBNC &&
> - hweight8(dev->supported_speeds) > 1)
> + hweight16(dev->supported_speeds) > 1)
> services |= PCIE_PORT_SERVICE_BWCTRL;
> }
>
> diff --git a/drivers/thermal/pcie_cooling.c b/drivers/thermal/pcie_cooling.c
> index a876d64f15827..9a2e39398674b 100644
> --- a/drivers/thermal/pcie_cooling.c
> +++ b/drivers/thermal/pcie_cooling.c
> @@ -75,6 +75,7 @@ static_assert(PCIE_SPEED_5_0GT + 1 == PCIE_SPEED_8_0GT);
> static_assert(PCIE_SPEED_8_0GT + 1 == PCIE_SPEED_16_0GT);
> static_assert(PCIE_SPEED_16_0GT + 1 == PCIE_SPEED_32_0GT);
> static_assert(PCIE_SPEED_32_0GT + 1 == PCIE_SPEED_64_0GT);
> +static_assert(PCIE_SPEED_64_0GT + 1 == PCIE_SPEED_128_0GT);
>
> MODULE_AUTHOR("Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>");
> MODULE_DESCRIPTION("PCIe cooling driver");
Once you start to use the new capability, you'll also need to check if the
GENMASK()s related to speed vector are still okay (both bwctrl and core
do it). There might also be fls() or something like that that which no
longer holds with the 0x7 reserved hole in the speeds but I didn't check.
--
i.