[PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants
From: Hugo Villeneuve
Date: Mon Mar 02 2026 - 14:11:55 EST
From: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>
Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be
reused on other boards.
This will simplify adding future dedicated device tree files for each CPU
variant.
Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other
boards.
Reorder pinctrl_gpio_leds to respect alphabetical order.
Signed-off-by: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>
---
arch/arm/boot/dts/nxp/imx/Makefile | 1 +
.../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 +
...ts => imx6ul-var-som-concerto-common.dtsi} | 17 +-
.../dts/nxp/imx/imx6ul-var-som-concerto.dts | 312 +-----------------
.../dts/nxp/imx/imx6ull-var-som-concerto.dts | 17 +
5 files changed, 33 insertions(+), 321 deletions(-)
copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts => imx6ul-var-som-concerto-common.dtsi} (95%)
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index de4142e8f3ce8..bc534d0fb1412 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-tarragon-slavext.dtb \
imx6ull-tqma6ull2-mba6ulx.dtb \
imx6ull-tqma6ull2l-mba6ulx.dtb \
+ imx6ull-var-som-concerto.dtb \
imx6ull-uti260b.dtb \
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 2072e8ba4d469..22b0c4e0725a5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
similarity index 95%
copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index d16e75164fd18..10a23ae104359 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -1,19 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
- * Variscite SoM mounted on it
+ * Variscite SoM mounted on it, for all CPU variants.
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
-#include "imx6ul-var-som.dtsi"
#include <dt-bindings/leds/common.h>
/ {
- model = "Variscite VAR-SOM-6UL Concerto Board";
- compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
-
chosen {
stdout-path = &uart1;
};
@@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059
>;
};
- pinctrl_gpio_leds: gpio-ledsgrp {
- fsl,pins = <
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
- >;
- };
-
pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059
>;
};
- pinctrl_i2c1: i2c1grp {
+ pinctrl_gpio_leds: gpio-ledsgrp {
fsl,pins = <
- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
>;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
index d16e75164fd18..11b45f105b7ad 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
@@ -1,320 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
- * Variscite SoM mounted on it
+ * Variscite SoM mounted on it (6UL CPU variant).
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
+/dts-v1/;
+
#include "imx6ul-var-som.dtsi"
-#include <dt-bindings/leds/common.h>
+#include "imx6ul-var-som-concerto-common.dtsi"
/ {
- model = "Variscite VAR-SOM-6UL Concerto Board";
+ model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
-
- chosen {
- stdout-path = &uart1;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
-
- key-back {
- gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_BACK>;
- };
-
- key-wakeup {
- gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "gpled2";
- gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&fec1 {
- status = "disabled";
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
- phy-mode = "rmii";
- phy-handle = <ðphy1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- clocks = <&rmii_ref_clk>;
- clock-names = "rmii-ref";
- reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- micrel,led-mode = <0>;
- micrel,rmii-reference-clock-select-25-mhz;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- rtc@68 {
- /*
- * To actually use this interrupt
- * connect pins J14.8 & J14.10 on the Concerto-Board.
- */
- compatible = "dallas,ds1337";
- reg = <0x68>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc>;
- interrupt-parent = <&gpio1>;
- interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&iomuxc {
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
- >;
- };
-
- pinctrl_enet2_gpio: enet2-gpiogrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
- >;
- };
-
- pinctrl_enet2_mdio: enet2-mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
- >;
- };
-
- pinctrl_gpio_key_back: gpio-key-backgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059
- >;
- };
-
- pinctrl_gpio_leds: gpio-ledsgrp {
- fsl,pins = <
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
- >;
- };
-
- pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
- >;
- };
-
- pinctrl_rtc: rtcgrp {
- fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
- MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
- MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
- MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_usb_otg1_id: usbotg1idgrp {
- fsl,pins = <
- MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
- >;
- };
-
- pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0
- >;
- };
-};
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "disabled";
-};
-
-&snvs_rtc {
- status = "disabled";
-};
-
-&tsc {
- /*
- * Conflics with wdog1 ext-reset-output & SD CD pins,
- * so we keep it disabled by default.
- */
- status = "disabled";
-};
-
-/* Console UART */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* ttymxc4 UART */
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg1_id>;
- dr_mode = "otg";
- disable-over-current;
- srp-disable;
- hnp-disable;
- adp-disable;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
- cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- keep-power-in-suspend;
- wakeup-source;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- /*
- * To actually use ext-reset-output
- * connect pins J17.3 & J17.8 on the Concerto-Board
- */
- fsl,ext-reset-output;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
new file mode 100644
index 0000000000000..7c601af2657d7
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
+ * Variscite SoM mounted on it (6ULL CPU variant).
+ *
+ * Copyright 2026 Dimonoff
+ */
+
+/dts-v1/;
+
+#include "imx6ull-var-som.dtsi"
+#include "imx6ul-var-som-concerto-common.dtsi"
+
+/ {
+ model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
+ compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
+};
--
2.47.3