Re: [PATCH] iommu/amd: Adhere to IVINFO[VASIZE] for address limits

[Jason Gunthorpe]

On Fri, Feb 27, 2026 at 04:58:04PM +0000, Ankit Soni wrote:
> +static u8 ivinfo_vasize_bits(void)
> +{
> +	u8 vasize;
> +
> +	vasize = FIELD_GET(IOMMU_IVINFO_VASIZE, amd_iommu_ivinfo);
> +
> +	/*
> +	 * IVINFO[VASIZE] encodes the log2 of the maximum virtual address
> +	 * processed by the IOMMU.
> +	 */
> +	switch (vasize) {
> +	case 32:
> +	case 40:
> +	case 48:
> +	case 64:
> +		return vasize;
> +	default:
> +		pr_warn_once("IVRS: IVINFO[VASIZE]=0x%x is invalid, defaulting to 64‑bit VA\n",
> +			     vasize);
> +		return 64;

Why check and limit it like this? 

> -	cfg.common.hw_max_vasz_lg2 =
> -		min(64, (amd_iommu_hpt_level - 1) * 9 + 21);
> +	cfg.common.hw_max_vasz_lg2 = amd_iommu_hpt_vasize;

This has no restriction, you can send it whatever size you want.

Shouldn't the v2 side respect this too? If there is some reason why
not it would be good to include it in a comment.

Jason