Re: [PATCH kernel 4/9] dma/swiotlb: Stop forcing SWIOTLB for TDISP devices

[dan.j.williams]

Jason Gunthorpe wrote:
[..]
> > I have a v2 of a TEE I/O set going out shortly and sounds like it will
> > need a rethink for this attribute proposal for v3. I think it still helps to
> > have combo sets at this stage so the whole lifecycle is visible in one
> > set, but it is nearly at the point of being too big a set to consider in
> > one sitting.
> 
> My problem is I can't get in one place an actually correct picture of
> how the IOVA translation works in all the arches and how the
> phys_addr_t works.
> 
> So it is hard to make sense of all these proposals. What I would love
> to see is one series that deals with this:
> 
>   [PATCH v2 11/19] x86, dma: Allow accepted devices to map private memory
> 
> For *all* the arches, along with a description for each of:
>  * how their phys_addr_t is constructed
>  * how their S2 IOMMU mapping works
>  * how a vIOMMU S1 would change any of the above.
> 
> Then maybe we can see if we are actually doing it properly or not.

Yes, this is my struggle as well. I will put this on the agenda for the
next CCC call.

[..]
> 
> I'm surprised because Xu said:
> 
>  This is same as Intel TDX, the GPA shared bit are used by IOMMU to
>  target shared/private. You can imagine for T=1, there are 2 IOPTs, or
>  1 IOPT with all private at lower address & all shared at higher address.
> 
>  https://lore.kernel.org/all/aaF6HD2gfe%2Fudl%2Fx@yilunxu-OptiPlex-7050/
> 
> So how come that not have exactly the same problem as ARM?

Sorry, yes TDX has same behavior as ARM, excuse the noise.