Re: [PATCH v2 3/3] clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}

[Geert Uytterhoeven]

Hi Fabrizio,

On Tue, 3 Feb 2026 at 13:43, Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
> The HW user manual for the Renesas RZ/V2H(P) SoC specifies
> that only the WDT1 IP is supposed to be used by Linux,
> while the WDT{0,2,3} IPs are supposed to be used by the CM33
> and CR8 cores.
>
> Remove the clock and reset entries for WDT{0,2,3} to prevent
> interfering with the CM33 and CR8 cores.
>
> This change is harmless as only WDT1 is used by Linux, there
> are no users for the WDT{0,2,3} cores.
>
> Fixes: 3aeccbe08171 ("clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT")
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-fixes for v7.0.

Apparently the same applies to RZ/V2N.  Shall I just apply this patch
to drivers/clk/renesas/r9a09g056-cpg.c, too, with the SoC name
and part number updated, and

    Fixes: e018f9f8973760fa ("clk: renesas: r9a09g056: Add clock and
reset entries for WDT controllers")

?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds