Re: [PATCH v2 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS
From: Odelu Kukatla
Date: Tue Mar 03 2026 - 09:50:44 EST
On 2/12/2026 4:32 PM, Krzysztof Kozlowski wrote:
> On Wed, Feb 11, 2026 at 02:41:10PM +0530, Odelu Kukatla wrote:
>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>> inside a block whose interface is clock-gated. For that node,
>> driver must enable the corresponding clock(s) before accessing
>> the registers. Add the 'clocks' property so the driver can obtain
>> and enable the required clock(s).
>>
>> Only interconnects that have clock‑gated QoS register interface
>> use this property; it is not applicable to all interconnect nodes.
>>
>> Signed-off-by: Odelu Kukatla <odelu.kukatla@xxxxxxxxxxxxxxxx>
>> ---
>> .../interconnect/qcom,qcs615-rpmh.yaml | 46 +++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> index e06404828824..42679deb4607 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> @@ -34,6 +34,10 @@ properties:
>> reg:
>> maxItems: 1
>>
>> + clocks:
>> + minItems: 4
>> + maxItems: 4
>
> Define the clocks here please.
>
>> +
>> required:
>> - compatible
>>
>> @@ -53,6 +57,37 @@ allOf:
>> required:
>> - reg
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,qcs615-aggre1-noc
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: aggre UFS PHY AXI clock
>> + - description: aggre USB2 SEC AXI clock
>> + - description: aggre USB3 PRIM AXI clock
>> + - description: RPMH CC IPA clock
>
> And this entire "if" goes away... unless you already plan to correct other
> devices. If so, please correc them now.
>
Hi Krzysztof,
Thanks for the review.
I will move the clocks definition to the top-level properties and remove
the specific if block for aggre1-noc as suggested.
Regarding the exclusion “if” block: I will keep it to align with your
recent fix for SA8775P (dt-bindings: interconnect: sa8775p: Fix
incorrectly added reg and clocks) where you enforced strict constraints.
My plan for v3 is to:
1.Define clocks at the top level.
2.Remove "if" block for aggre1-noc
3.Keep "if" block to explicitly disallow clocks for the nodes that do
not support them.
I will send v3 with these changes shortly.
Regards,
Odelu
> Best regards,
> Krzysztof
>