Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

[Bryan O'Donoghue]

On 03/03/2026 18:58, Vijay Kumar Tumati wrote:
> > > - TITAN_TOP_GDSC
> > > - MXC
> > > - MMCX
> > > - MXA - first time I've heard of this rail, from memory I don't remember
> > >          having seen this in ipcat when I could do so.
> > MCX and MMCX are comminly required power domains across the PHYs but a 
> > subset of PHYs have the dependency on MXA.
> Actually, it's a bit more complicated on this target as 
> cam_cc_cphy_rx_clk_src also depends on MXA, which means all the CBCs 
> connected this RCG do as well.

Right but that's something to model in the clock-controller then not the 
PHY.

i.e. if a clock depends on MXA then the clock controller should 
represent that dependency - not the PHY that depends on the clock.

camcc on hamoa looks like this

                camcc: clock-controller@ade0000 {
                        compatible = "qcom,x1e80100-camcc";
                        reg = <0 0x0ade0000 0 0x20000>;
                        clocks = <&gcc GCC_CAMERA_AHB_CLK>,
                                 <&bi_tcxo_div2>,
                                 <&bi_tcxo_ao_div2>,
                                 <&sleep_clk>;
                        power-domains = <&rpmhpd RPMHPD_MXC>,
                                        <&rpmhpd RPMHPD_MMCX>;
                        required-opps = <&rpmhpd_opp_low_svs>,
                                        <&rpmhpd_opp_low_svs>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;
                };

So... we may need to add MXA here, probably do based on what you've said 
but I believe TITAN_TOP_GDSC is the only power-domain we need to list 
for the PHYs themselves, as what you've described above is a clock power 
dependency which we basically already capture in the clock controller - 
absent the MXA - which is apparently always on...

Sidenote, is MXA required for videocc too ?

                videocc: clock-controller@aaf0000 {
                        compatible = "qcom,x1e80100-videocc";
                        reg = <0 0x0aaf0000 0 0x10000>;
                        clocks = <&bi_tcxo_div2>,
                                 <&gcc GCC_VIDEO_AHB_CLK>;
                        power-domains = <&rpmhpd RPMHPD_MMCX>,
                                        <&rpmhpd RPMHPD_MXC>;
                        required-opps = <&rpmhpd_opp_low_svs>,
                                        <&rpmhpd_opp_low_svs>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;
                };

---
bod