Re: [PATCH v1] x86/cpu/topology: Consolidate AMD and Hygon cases in parse_topology()

[Wei Wang]

On 3/4/26 5:45 AM, Christian Ludloff wrote:
> > Merge the two separate switch cases for AMD and Hygon
> > as they share the common cpu_parse_topology_amd().
>
> On a tangential note, it appears as if there actually are
> differences between AMD and Hygon when it comes to
> the definition of CPUID return values... and MSRs, too.
>
> For example:
>
> https://web.archive.org/web/20250814085228/https://gitee.com/anolis/cloud-kernel/blob/devel-5.10/Documentation/x86/hygon-secure-virtualization.rst
>
> 0x8000001f[eax]:
>          Bit[30]   indicates support for CSV
>
> 0xc0010131:
>          Bit[30]   0 = CSV is not active
>                    1 = CSV is active
>
> For AMD, that CPUID bit is HvInUseWrAllowed instead.
> For AMD, that MSR bit is reserved, and does fault for 1.
>
> So consolidation efforts need to be undertaken with care.

Yes, AMD and Hygon do diverge in several CPUID/MSR definitions, 
including the CSV-related bits you pointed out. Those differences 
definitely need to be kept in mind when touching feature‑related
code.

For parse_topology(), though, both vendors already use the same CPUID 
leaves for topology enumeration, and the existing code routes both 
through cpu_parse_topology_amd() here. I’m not aware of any 
topology‑related divergence between AMD and Hygon, and the current 
implementation treats them identically. Given that, merging the two 
switch cases avoids duplication, similar to how CENTAUR and ZHAOXIN
are handled.