[PATCH 4/4] riscv: dts: spacemit: k3: add full resource to UART
From: Yixun Lan
Date: Wed Mar 04 2026 - 02:40:27 EST
Previously the UART rely on external bootloader to initialize clock,
pinctrl and reset, to solve this, explicitly adding those resource in
Device Tree, so UART driver will handle them properly.
Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++++++++------
3 files changed, 68 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b691304d4b74..b098dbd0e7a1 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -5,6 +5,7 @@
*/
#include "k3.dtsi"
+#include "k3-pinctrl.dtsi"
/ {
model = "SpacemiT K3 Pico-ITX";
@@ -25,5 +26,7 @@ memory@100000000 {
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_0_cfg>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
new file mode 100644
index 000000000000..efb0f1572188
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026 Yixun Lan <dlan@xxxxxxxxxx>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K3_PADCONF(pin, func) (((pin) << 16) | (func))
+
+/* Map GPIO pin to each bank's <index, offset> */
+#define K3_GPIO(x) (x / 32) (x % 32)
+
+&pinctrl {
+ /omit-if-no-ref/
+ uart0_0_cfg: uart0-0-cfg {
+ uart0-0-pins {
+ pinmux = <K3_PADCONF(149, 2)>, /* uart0 tx */
+ <K3_PADCONF(150, 2)>; /* uart0 rx */
+
+ bias-pull-up = <0>;
+ drive-strength = <25>;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 3683a1a65362..a3a8ceddabec 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/spacemit,k3-clocks.h>
+#include <dt-bindings/reset/spacemit,k3-resets.h>
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
@@ -451,7 +452,10 @@ uart0: serial@d4017000 {
reg = <0x0 0xd4017000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART0>,
+ <&syscon_apbc CLK_APBC_UART0_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART0>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -461,7 +465,10 @@ uart2: serial@d4017100 {
reg = <0x0 0xd4017100 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART2>,
+ <&syscon_apbc CLK_APBC_UART2_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART2>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -471,7 +478,10 @@ uart3: serial@d4017200 {
reg = <0x0 0xd4017200 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART3>,
+ <&syscon_apbc CLK_APBC_UART3_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART3>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -481,7 +491,10 @@ uart4: serial@d4017300 {
reg = <0x0 0xd4017300 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART4>,
+ <&syscon_apbc CLK_APBC_UART4_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART4>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -491,7 +504,10 @@ uart5: serial@d4017400 {
reg = <0x0 0xd4017400 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART5>,
+ <&syscon_apbc CLK_APBC_UART5_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART5>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -501,7 +517,10 @@ uart6: serial@d4017500 {
reg = <0x0 0xd4017500 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART6>,
+ <&syscon_apbc CLK_APBC_UART6_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART6>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -511,7 +530,10 @@ uart7: serial@d4017600 {
reg = <0x0 0xd4017600 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART7>,
+ <&syscon_apbc CLK_APBC_UART7_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART7>;
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -521,7 +543,10 @@ uart8: serial@d4017700 {
reg = <0x0 0xd4017700 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART8>,
+ <&syscon_apbc CLK_APBC_UART8_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART8>;
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -531,7 +556,10 @@ uart9: serial@d4017800 {
reg = <0x0 0xd4017800 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART9>,
+ <&syscon_apbc CLK_APBC_UART9_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART9>;
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -567,7 +595,10 @@ uart10: serial@d401f000 {
reg = <0x0 0xd401f000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
- clock-frequency = <14700000>;
+ clocks = <&syscon_apbc CLK_APBC_UART10>,
+ <&syscon_apbc CLK_APBC_UART10_BUS>;
+ clock-names = "core", "bus";
+ resets = <&syscon_apbc RESET_APBC_UART10>;
interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
--
2.53.0