Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Krzysztof Kozlowski]

On 04/03/2026 16:18, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
> Thanks for the review.
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
>> Sent: 04 March 2026 15:04
>> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
>>
>> On 04/03/2026 08:49, Biju wrote:
>>> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>>>
>>> Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible
>>> with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>>> ---
>>>  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
>>>  1 file changed, 26 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> index cf8b733b766d..599c06ff08e5 100644
>>> --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> @@ -13,6 +13,7 @@ properties:
>>>    compatible:
>>>      oneOf:
>>>        - enum:
>>> +          - renesas,r9a08g046-rspi # RZ/G3L
>>>            - renesas,r9a09g057-rspi # RZ/V2H(P)
>>>            - renesas,r9a09g077-rspi # RZ/T2H
>>>        - items:
>>> @@ -85,6 +86,31 @@ required:
>>>
>>>  allOf:
>>>    - $ref: spi-controller.yaml#
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - renesas,r9a08g046-rspi
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          maxItems: 2
>>> +
>>> +        clock-names:
>>> +          items:
>>> +            - const: pclk
>>> +            - const: tclk
>>> +        dmas:
>>> +          maxItems: 2
>>> +
>>> +        dma-names:
>>> +          maxItems: 2
>>
>> So even after my objections here:
>> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@xxxxxxxxxx/
>>
>> this was not fixed and Renesas did not provide actual cross-patch review.
> 
> That patch is not correct. See below.
> 
>>
>> This is still probably wrong as pointed out by other patches by Renesas.
>> Also, you cannot have flexible names.
> 
> You can have "rx", "tx" in any order and {rx, tx} should be unique dma specifier

No. You cannot. I just told you so. Please read writing-bindings for
arguments.

Look at the code which was here before that incomplete solution was merged.



> and  it should have at least 1 tx and 1 rx for multiple DMAC.
> 
> For RZ/G3L SoC, only 1 DMA and Nothing prevent us to specify it as { rx, tx} or {rx, tx}
> 

Well, I prevent you. So NAK.

Best regards,
Krzysztof