[PATCH v2 0/2] selftests/arm64: Fix sve2p1_sigill() and add cmpbr_sigill() for hwcap test

[Yifan Wu]

Hi all,

This patch series fixes and adds two selftests in the arm64 hwcap
test suite.

Patch 1/2 fixes the sve2p1_sigill() test to correctly detect the
FEAT_SVE2p1 feature. Previously, the test incorrectly assumed that
the presence of FEAT_SVE2.1 implied support for the BFADD
instruction, which actually depends on the FEAT_SVE_B16B16 feature.
The test is updated to use the LD1Q instruction, which is
unambiguously implied by FEAT_SVE2p1.

Patch 2/2 implements the cmpbr_sigill() test to correctly detect
the presence of the CMPBR extension. The test uses the CBEQ
instruction, which is valid only if the CPU supports the extension.
If supported, a branch is taken and the UDF instruction is skipped,
avoiding a SIGILL. Otherwise, the UDF is executed and a SIGILL
is generated.

These changes improve the accuracy and reliability of the selftests
for arm64 hardware capability detection.

References:

CBEQ: https://developer.arm.com/documentation/ddi0602/2025-12/Base-Instructions/CB-cc---register---Compare-registers-and-branch-?lang=en
BFADD: https://developer.arm.com/documentation/ddi0602/2025-12/SVE-Instructions/BFADD--unpredicated---BFloat16-add--unpredicated--?lang=en
LD1Q: https://developer.arm.com/documentation/ddi0602/2025-12/SVE-Instructions/LD1Q--Gather-load-quadwords-?lang=en
ID_AA64ZFR0_EL1: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/ID-AA64ZFR0-EL1--SVE-Feature-ID-Register-0?lang=en

Change Log:
v1:
Fixes the sve2p1_sigill() in patch 1.
Implements cmpbr_sigill() by the single asm volatile statement.
Updated the comments.

v1 can be found at:
https://lore.kernel.org/all/20260227031933.4103333-1-wuyifan50@xxxxxxxxxx/

Yifan Wu (2):
  selftest/arm64: Fix sve2p1_sigill() to hwcap test
  selftests/arm64: Implement cmpbr_sigill() to hwcap test

 tools/testing/selftests/arm64/abi/hwcap.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

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2.33.0