Re: [PATCH v3 06/10] clk: renesas: Add support for RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Tue, 17 Feb 2026 at 12:13, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > From: Biju <biju.das.au@xxxxxxxxx>
> > The clock structure for RZ/G3L is almost identical to RZ/G3S SoC with more IP blocks such as LCDC,
> > CRU, LVDS and GPU.
> >
> > Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and binds
> > it with the RZ/G2L CPG core driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Thanks for your patch!

> > --- /dev/null
> > +++ b/drivers/clk/renesas/r9a08g046-cpg.c

> > +enum clk_ids {
> > +     /* Core Clock Outputs exported to DT */
> > +     LAST_DT_CORE_CLK = R9A08G046_CLK_P4_DIV2,

This will probably have to change, as per my comments on the DT
binding definitions.

> > +/* Divider tables */
> > +static const struct clk_div_table dtable_4_128[] = {
> > +     { 0, 4 },
> > +     { 1, 2 },
>
> Typo 2->8

Indeed.

> > +       .num_resets = R9A08G046_LVDS_RESET_N + 1, /* Last reset ID + 1 */

This may need to change, too.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds