Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
> Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
> compared to 1 clock on other SoCs.
>
> Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module

Core Clocks, as listed in section 4.4.1 ("Block Diagram of the Clock System")

> clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
> Reset definitions referring to registers CPG_RST_* in Section 4.4.3
> ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
>
> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -28,19 +28,30 @@ properties:
>        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
>        - renesas,r9a07g054-cpg # RZ/V2L
>        - renesas,r9a08g045-cpg # RZ/G3S
> +      - renesas,r9a08g046-cpg # RZ/G3L
>        - renesas,r9a09g011-cpg # RZ/V2M
>
>    reg:
>      maxItems: 1
>
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Clock source to CPG can be either from external clock
> +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> +      - description: ETH0 TXC clock input
> +      - description: ETH0 RXC clock input
> +      - description: ETH1 TXC clock input
> +      - description: ETH1 RXC clock input
>
>    clock-names:
> -    description:
> -      Clock source to CPG can be either from external clock input (EXCLK) or
> -      crystal oscillator (XIN/XOUT).
> -    const: extal
> +    minItems: 1
> +    items:
> +      - const: extal
> +      - const: eth0_txc_tx_clk
> +      - const: eth0_rxc_rx_clk
> +      - const: eth1_txc_tx_clk
> +      - const: eth1_rxc_rx_clk

Are you sure about these four clocks? On which pins are they input?

>
>    '#clock-cells':
>      description: |

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> @@ -0,0 +1,343 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A08G046 CPG Core Clocks */

[...]

> +#define R9A08G046_OSCCLK               52
> +#define R9A08G046_OSCCLK2              53
> +#define R9A08G046_CLK_P4_DIV2          54

CLK_P4_DIV2 looks like a purely internal clock to me.


> +
> +/* R9A08G046 Module Clocks */

[...]

> +#define R9A08G046_CRU_PCLK             65
> +#define R9A08G046_CRU_ACLK             66
> +#define R9A08G046_MIPI_DSI_PLLCLK      67

MIPI_DSI_PLLCLK is indeed not a gateable clock, so it should be a core
clock.

> +#define R9A08G046_MIPI_DSI_SYSCLK      68
> +#define R9A08G046_MIPI_DSI_ACLK                69
> +#define R9A08G046_MIPI_DSI_PCLK                70
> +#define R9A08G046_MIPI_DSI_VCLK                71
> +#define R9A08G046_MIPI_DSI_LPCLK       72
> +#define R9A08G046_LVDS_PLLCLK          73
> +#define R9A08G046_LVDS_CLK_DOT0                74
> +#define R9A08G046_LVDS_PCLK            75

LVDS_PCLK does not seem to exist, there is only a single reference to it
(but I can see where its gate bit used to be ;-)

> +#define R9A08G046_LCDC_CLK_A           76
> +#define R9A08G046_LCDC_CLK_D           77
> +#define R9A08G046_LCDC_CLK_P           78
> +#define R9A08G046_SSI0_PCLK2           79
> +#define R9A08G046_SSI0_PCLK_SFR                80
> +#define R9A08G046_SSI1_PCLK2           81
> +#define R9A08G046_SSI1_PCLK_SFR                82
> +#define R9A08G046_SSI2_PCLK2           83
> +#define R9A08G046_SSI2_PCLK_SFR                84
> +#define R9A08G046_SSI3_PCLK2           85
> +#define R9A08G046_SSI3_PCLK_SFR                86
> +#define R9A08G046_USB_U2H0_HCLK                87
> +#define R9A08G046_USB_U2H1_HCLK                88
> +#define R9A08G046_USB_U2P0_EXR_CPUCLK  89
> +#define R9A08G046_USB_U2P1_EXR_CPUCLK  90
> +#define R9A08G046_USB_PCLK             91
> +#define R9A08G046_USB_SCLK             92

USB_SCLK is not gateable, so it should be a core clock.

[...]

> +/* R9A08G046 Resets */

[...]

> +#define R9A08G046_RSCI2_TRESETN                114
> +#define R9A08G046_RSCI3_TRESETN                115
> +#define R9A08G046_LVDS_RESET_N         116

Missing BSC_X_PRESET_BSC?
It could be added later, but you do list the corresponding module clock.

> +
> +#endif /* __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ */


The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds