Re: [PATCH v2 7/8] drm/msm/dpu: Add support for Eliza SoC

[Dmitry Baryshkov]

On Wed, Mar 04, 2026 at 04:29:43PM +0200, Dmitry Baryshkov wrote:
> On Wed, Mar 04, 2026 at 01:58:49PM +0100, Krzysztof Kozlowski wrote:
> > Add support for DPU (v12.4) on Qualcomm Eliza SoC, with one
> > incomplete/skipped part: HDMI interface (INT_4).
> > 
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> > 
> > ---
> > 
> > Changes in v2:
> > 1. Drop stale comment
> > 2. Fix INTF_3 controller_id -> DP0 (Dmitry)
> > ---
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h | 365 +++++++++++++++++++++
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
> >  4 files changed, 368 insertions(+)
> > 
> > +	}, {
> > +		.name = "intf_3", .id = INTF_3,
> > +		.base = 0x37000, .len = 0x4bc,
> > +		.type = INTF_DP,
> 
> This should be INTF_NONE until we support MST.

After checking more, this is fine.


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>



> 
> > +		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
> > +		.prog_fetch_lines_worst_case = 24,
> > +		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> > +		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> > +	}
> > +};
> > +
> 
> -- 
> With best wishes
> Dmitry

-- 
With best wishes
Dmitry