Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600

[Christian Ludloff]

Tony,

can you confirm whether F=6 M=1F is affected or not?
(Supposedly that's ZX-D... but the F in the model does
make me wonder/ask.)

Presumably the 6FE and 10690 microcodes which are
out in the wild do not fix the bug, correct?

000006fe_00000000_20110809_8f396f73
000006fe_00000000_20110809_8f397072
000006fe_00000001_20160525_7214d1e1
000006fe_00000001_20170109_25646399
000006fe_00000001_20180726_6e07329b
000006fe_00000001_20180726_6e1e984b

00010690_00000000_20110809_259878a5
00010690_00000001_20160525_3c34fc1a
00010690_00000001_20170109_a8b24dc2
00010690_00000001_20180726_0c55f25d
00010690_00000001_20180726_41faefde

As for making the code conditional for Centaur/Zhaoxin,
stepping E seems to be when FSGSBASE arrived – and
while there are CPUID dumps for 6FE that say VIA Eden
it is possible that they too have the bug.

As for making the code conditional for Zhaoxin models in
the string, that would require more than just C4600 – the
collection of known dumps includes others.

--
C.