[PATCH v5 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle

From: Neeraj Soni

Date: Fri Mar 06 2026 - 04:34:14 EST


Starting with sc7280(kodiak), the ICE will have its own device-tree node.
So add the qcom,ice property to reference it.

To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE
register region in the SDHCI node. Older SoCs without ICE remain valid as
no additional requirement is imposed.

Co-developed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@xxxxxxxxxxxxxxxx>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@xxxxxxxxxxxxxxxx>
Signed-off-by: Neeraj Soni <neeraj.soni@xxxxxxxxxxxxxxxx>

---

Some initial work is done by Abel here:
https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@xxxxxxxxxx/
and by Abhinaba here:
https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-1-2a34d8d03c72@xxxxxxxxxxxxxxxx/

This patch adds the purpose and usage for phandle in the description and encodes
it properly in the schema.
---
.../devicetree/bindings/mmc/sdhci-msm.yaml | 95 +++++++++++++------
1 file changed, 67 insertions(+), 28 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 938be8228d66..cc9f7724bdf0 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -140,6 +140,11 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.

+ qcom,ice:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
+
iommus:
minItems: 1
maxItems: 8
@@ -193,35 +198,69 @@ allOf:
enum:
- qcom,sdhci-msm-v4
then:
- properties:
- reg:
- minItems: 2
- items:
- - description: Host controller register map
- - description: SD Core register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 2
- items:
- - const: hc
- - const: core
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ - const: ice
else:
- properties:
- reg:
- minItems: 1
- items:
- - description: Host controller register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 1
- items:
- - const: hc
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ - const: ice

unevaluatedProperties: false

--
2.34.1