[PATCH 0/3] Add critical resets support to RZ/G2L SoC family

[Biju]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Some reset lines must remain deasserted at all times after boot, as
asserting them would disable critical system functionality with no
owning driver to restore them. This mirrors the existing crit_mod_clks
mechanism which protects critical module clocks from being disabled.

On RZ/G2L family SoCs, DMA reset to be deasseted for routing some
peripheral interrupts to CPU.

After a suspend/resume cycle, critical module clocks may be left
disabled as the hardware state is not automatically restored. Unlike
regular clocks which are re-enabled by their respective drivers, critical
clocks (CLK_IS_CRITICAL) have no owning driver to restore them, so the
CPG driver must take responsibility for re-enabling them on resume.

Biju Das (3):
  clk: renesas: rzg2l-cpg: Add support for critical resets
  clk: renesas: r9a07g04{3,4}/r9a08g045-cpg: Add critical reset entries
  clk: renesas: rzg2l-cpg: Re-enable critical module clocks during
    resume

 drivers/clk/renesas/r9a07g043-cpg.c |  8 +++
 drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++
 drivers/clk/renesas/r9a08g045-cpg.c |  9 ++++
 drivers/clk/renesas/rzg2l-cpg.c     | 75 ++++++++++++++++++++++++++++-
 drivers/clk/renesas/rzg2l-cpg.h     |  7 +++
 5 files changed, 111 insertions(+), 1 deletion(-)

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2.43.0