Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts

[Samiullah Khawaja]

On Fri, Mar 06, 2026 at 04:03:21PM -0400, Jason Gunthorpe wrote:
> On Fri, Mar 06, 2026 at 07:59:33PM +0000, Samiullah Khawaja wrote:
> > On Fri, Mar 06, 2026 at 03:43:12PM -0400, Jason Gunthorpe wrote:
> > > On Fri, Mar 06, 2026 at 07:35:19PM +0000, Samiullah Khawaja wrote:
> > > > On Fri, Mar 06, 2026 at 09:00:06AM -0400, Jason Gunthorpe wrote:
> > > > > On Fri, Mar 06, 2026 at 11:22:52AM +0800, Baolu Lu wrote:
> > > > > > I believe this issue is not unique to the arm-smmu-v3 driver. Device ATC
> > > > > > invalidation timeout is a generic challenge across all IOMMU
> > > > > > architectures that support PCI ATS. Would it be feasible to implement a
> > > > > > common 'fencing and recovery' mechanism in the IOMMU core so that all
> > > > > > IOMMU drivers could benefit?
> > > > >
> > > > > I think yes, for parts, but the driver itself has to do something deep
> > > > > inside it's invalidation to allow the flush to complete without
> > > > > exposing the system to memory corruption - meaning it has to block
> > > > > translated requests before completing the flush
> > > >
> > > > Yes and currently the underlying drivers have software timeouts
> > > > (AMD=100millisecond, arm-smmu-v3=1second) defined which could timeout
> > > > before the actual ATC invalidation timeout occurs. Do you think maybe
> > > > the timeout needs to be propagated to the caller (flush callback) so the
> > > > memory/IOVA is not allocated to something else?
> > >
> > > No, definitely not, that's basically impossible, so many callers just
> > > can't handle such an idea, and you can't ever fully recover from such
> > > a thing.
> > >
> >
> > Agreed.
> > > > Or blocking translated requests for such devices should be enough?
> > >
> > > Yes, we have to fence the hardware and then allow the existing SW
> > > stack to continue without any fear of UAF from the broken HW.
> >
> > And this applies to software timeout also I think, since both have same
> > end result.
>
> Any situation where the ATC flush doesn't get a positive response from
> the HW must fence the HW before continuing to avoid UAF bugs.
>
> Obviously today we just succeed the flush anyhow and hope for the
> best, and I think that is a good starting point for VT-d. We need at
> least that to build anything more complex on to.
>
> Fencing the device also has to come with a full RAS flow to eventually
> unfence it, so I wouldn't do it in isolation.

But do you think doing the timeout logic without fencing would be good
enough? Currently VT-d blocks itself, until it gets an Invalidation
Timeout from HW, and system ends up in a hardlockup since interrupts are
disabled.

Are you concerned that if fencing is done without an RAS flow, the
device might not be able to detect the failure (if it really needs ATS
to work)?

I am thinking, we can do translated fence and timeout change for VT-d.
And the device can use existing RAS mechanism to recover itself. This
way we atleast make sure that caller of flush can reuse the memory/IOVAs
without UAFs.
> I would like the unfence to be done with a fresh domain attach (or
> re-attach I guess) that just rewrites the context entry with the
> correct one.

Agreed.
> For VT-d that probably also means it will need all the domain attach
> fixing we've talked about as a precondition too.
>
> Jason