Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Brian Masney]

On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo <mitltlatltl@xxxxxxxxx> wrote:
> On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@xxxxxxxxxx> wrote:
> > On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> > > On 3/3/26 12:55 PM, Pengyu Luo wrote:
> > > > From: White Lewis <liu224806@xxxxxxxxx>
> > > >
> > > > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> > > > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> > > > byte_intf_clk, the rate-change propagates through the divider up to the
> > > > parent PLL (byte_clk_src), halving the byte clock rate.
> > > >
> > > > A simiar issue had been also encountered on SM8750.
> > > > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> > > >
> > > > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> > > > so that clk_set_rate() on the divider adjusts only the divider ratio,
> > > > leaving the parent PLL untouched.
> > > >
> > > > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> > > > Signed-off-by: White Lewis <liu224806@xxxxxxxxx>
> > > > [pengyu: reword]
> > > > Signed-off-by: Pengyu Luo <mitltlatltl@xxxxxxxxx>
> > > > ---
> > >
> > > Looks like more platforms have this issue.. thanks for fixing this
> >
> > I hope within the next week to post a new draft of my patch series to
> > keep certain clk rates intact when sibling and parent rate changes occur
> > [1]. This will be for certain critical clks, such as the ones used for
> > DRM and sound. I have it working with kunit, and just need to clean up
> > some of my new clk helpers and commit messages before I post a v5.
> >
> > I'd like to test this on some real hardware and I have the Thinkpad x13s
> > with the sc8280xp SoC. Can this issue be reproduced on this hardware? If
> > so, can you provide me detailed instructions about how to trigger this
> > scenario?
> >
>
> Quick answer, no, x13s uses a edp panel, not dsi. This issue is
> related to dsi clks.

I posted my latest clk scaling work in an attempt to address the
underlying issue here.

https://lore.kernel.org/linux-clk/20260306-clk-scaling-v5-0-d21b84ee6f27@xxxxxxxxxx/T/#t

Feedback welcome!

Brian