Re: [PATCH v2 3/3] KVM: SVM: Advertise Translation Cache Extensions to userspace

[Sean Christopherson]

On Mon, Mar 09, 2026, Yosry Ahmed wrote:
> On Fri, Mar 6, 2026 at 5:54 PM Andrew Cooper <andrew.cooper3@xxxxxxxxxx> wrote:
> >
> > > From: Venkatesh Srinivas <venkateshs@xxxxxxxxxxxx>
> > >
> > > TCE augments the behavior of TLB invalidating instructions (INVLPG,
> > > INVLPGB, and INVPCID) to only invalidate translations for relevant
> > > intermediate mappings to the address range, rather than ALL intermdiate
> > > translations.
> > >
> > > The Linux kernel has been setting EFER.TCE if supported by the CPU since
> > > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions"),
> > > as it may improve performance.
> > >
> > > KVM does not need to do anything to virtualize the feature, only
> > > advertise it and allow setting EFER.TCE. If a TLB invalidating
> > > instruction is not intercepted, it will behave according to the guest's
> > > setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwise,
> > > KVM's emulation may invalidate more TLB entries, which is perfectly fine
> > > as the CPU is allowed to invalidate more TLB entries that it strictly
> > > needs to.
> > >
> > > Advertise X86_FEATURE_TCE to userspace, and allow the guest to set
> > > EFER.TCE if available.
> > >
> > > Signed-off-by: Venkatesh Srinivas <venkateshs@xxxxxxxxxxxx>
> > > Co-developed-by: Yosry Ahmed <yosry@xxxxxxxxxx>
> > > Signed-off-by: Yosry Ahmed <yosry@xxxxxxxxxx>
> >
> > I'll repeat what I said on that referenced patch.
> >
> > What's the point?  AMD have said that TCE doesn't exist any more; it's a
> > bit that's no longer wired into anything.
> >
> > You've got to get to pre-Zen hardware before this has any behavioural
> > effect, at which point the breath of testing is almost 0.
> 
> Oh, I did not know that, thanks for pointing it out.
> 
> I'll leave it up to Sean whether to pick this up (because Linux guests
> still set the bit), just pick up patches 1-2 as cleanups, or drop this
> entirely.

I'll grab 1-2 and leave 3 alone, at least for now.  It _should_ do no harm, but
it would really suck to discover that pre-Zen hardware has a TLB bug that affects
TCE, or worse, affects TCE but only for ASID!=0 translations or something.

If new CPUs ever use TCE, it'll be trivial to enable at that time.